An increase in a data rate of signal transmission and reception inside and outside an apparatus has been desired in relation to the improvement in performance of information processing apparatuses such as an apparatus for trunk communications and a server. A further increase in a bit rate has been desired in, for example, the field of high-speed I/O for transmitting and receiving signals in an integrated circuit chip and between chips (in an apparatus and between apparatuses) and the field of optical communication.
A reception circuit desirably determines transmitted data at an appropriate time and reproduces data and a clock (CDR: clock and data recovery). The CDR is realized by detecting a phase difference and a frequency difference between input data and a reception (sampling) clock and performing, based on information of the phase difference and the frequency difference, phase adjustment of the sampling clock. Among reception circuits, there is known a CDR circuit that retimes input data using a clock reproduced from the input data without using a reference clock and outputs data with reduced jitter.
It is known that the CDR circuit utilizes a phase detection circuit (a phase detector (PD)) that detects a phase difference between the input data and the clock. The CDR circuit using only the phase detector has a problem that a frequency range in which the clock is reproducible is narrow. Therefore, a CDR circuit utilizing a phase-frequency detection (phase frequency detector (PFD)) circuit that detects a frequency relation between the input data and the clock in addition to the phase difference between the input data and the clock is used.
The CDR circuit includes a feedback control circuit including an oscillator having a variable oscillation frequency (e.g., a voltage controlled oscillator (VCO)), a phase-frequency detection circuit, a charge pump (CP), and a loop filter (LPF). The filter LPF is a low pass filter. However, the filter LPF is included in a feedback loop, the filter LPF is called loop filter as well. The phase-frequency detection circuit detects a phase difference and a frequency relation between the input data and the clock and generates a phase difference signal and a frequency phase difference signal. The charge pump and the loop filter perform addition/subtraction of electric currents in accordance with phase difference information and frequency phase difference information and generate a control voltage of the VCO. In other words, the charge pump and the loop filter form a controller of the feedback control circuit. The VCO changes the oscillation frequency in accordance with the control voltage and outputs a clock. The generated clock is supplied to a decision circuit. The decision circuit captures input data in response to the clock, the time of which is adjusted with respect to the input data. The decision circuit may be formed as a part of the phase-frequency detection circuit.
Various phase-frequency detection circuits have been proposed. For example, for high-speed data reception, a differential phase-frequency detection circuit relatively small in circuit size including first and second phase detection circuits and a frequency phase detection circuit is widely used. The first phase detection circuit generates a clock phase control signal based on a phase relation between input data and a first clock. The first phase detection circuit is formed by, for example, two latch circuits, which latch the first clock at a change edge of the input data, and a multiplexer. An output of the multiplexer serves as a clock phase control signal. The second phase detection circuit includes a circuit configuration same as the circuit configuration of the first phase detection circuit and generates a clock phase detection signal based on a phase relation between input data and a second clock. The second clock has a frequency the same as the frequency of the first clock and has a phase different from the phase of the first clock by, for example, 90 degrees. The second clock is outputted from the VCO together with the first clock or is generated by phase-shifting the first clock with a phase shifter.
The frequency-phase detection circuit is formed by two latch circuits, which latch the clock phase detection signal outputted by the second phase detection circuit at a change edge of the clock phase control signal outputted by the first phase detection circuit, and a multiplexer. The multiplexer generates, from a direction of the change edge of the clock phase control signal and a latched value, a frequency phase signal indicating whether the frequency of the first clock is small or large with respect to the frequency of the input data. The frequency phase signal indicates +1 when the frequency of the first clock is small with respect to the frequency of the input data, indicates −1 when the frequency of the first clock is large with respect to the frequency of the input data, and indicates 0 when the frequency of the first clock is the same as the frequency of the input data. The clock phase control signal and the frequency phase signal are supplied to the charge pump. That is, the VCO is controlled based on the clock phase control signal and the frequency phase signal.
When the frequency difference between the input data and the first clock decreases and the input data and the first clock coincide with each other, the frequency phase signal becomes zero and the control of the VCO is not affected by the frequency phase signal. In other words, the VCO is controlled in accordance with only the clock phase control signal and the VCO is controlled to be in a state in which the input data and the first clock have a predetermined phase difference. This state is referred to as a lock state.
Providing a selector that performs switching is also proposed. The selector supplies the frequency phase signal to the charge pump until the frequency phase signal becomes zero and supplies the clock phase control signal to the charge pump after the frequency phase signal reaches a fixed value.
Even in the lock state, during reception of a signal having large jitter, the frequency phase signal may fluctuate and the frequency-phase detection circuit may malfunction and output a clock phase detection signal indicating that the frequencies of the input data and the first clock do not coincide with each other. When such a clock phase detection signal is inputted to the charge pump, the control of the VCO temporarily changes, and a loss-of-synchronization (unlock) error indicating that the frequency of the first clock is different from the frequency of the input data occurs.
In a normal lock state, the CDR circuit is controlled such that one change edge (a falling edge here) of the first clock coincides with a change edge of the input data. However, even when the other change edge (a rising edge) of the first clock coincides with the change edge of the input data, the CDR circuit has a metastable state in which the frequency phase signal is zero, and when the loss-of-synchronization error occurs, the CDR circuit may be in the metastable state.
Related techniques are disclosed in, for example, Japanese Laid-open Patent Publication Nos. 11-355111 (hereinafter referred to as Patent Literature 1), 2010-141594, 6-216765, and 2002-135093.
In addition, the related techniques are discussed in Ansgar Pottbacker, et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, December 1992 (hereinafter referred to as Non-Patent Literature 1).
Desired is a signal reproduction (CDR) circuit that is synchronization-error free and does not lose synchronization even in a lock state and even during reception of a signal having large jitter.